The present invention relates generally to memory devices with storage cells capable of storing more than one bit of data, i.e., more than two voltage levels. More particularly, the present invention is a memory device with storage cells capable of storing 1.5 bits of data, or three voltage levels, and methods using same.
Most conventional memory devices, including programmable read-only memory (PROM), electrically-erasable PROM (EEPROM), flash EEPROM, random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM) and the like, are capable of storing a single bit of data in a single memory cell. The memory cell of a conventional memory device may represent a data bit with a logical state of true or high voltage in the presence of stored charge in the memory cell. Conversely, the absence of charge may be representative of a data bit with a logical state false or low voltage.
Memory devices with more than one bit of data per cell are also known in the art. For example, U.S. Pat. No. 5,043,940 to Harrari defines multilevel states in a single memory cell in terms of the threshold voltage V1 of a split-channel flash EEPROM memory cell. Harrari discloses using four discrete voltage levels to store two bits of data per memory cell by applying multiple programming pulses to each memory cell. U.S. Pat. No. 5,163,021 to Mehrota et al. also discloses a multi-level memory system wherein each memory cell is capable of four threshold voltage levels.
U.S. Pat. No. 5,566,125 to Fazio et al. discloses a method and circuitry for storing discrete amounts of charge in a single flash memory cell. Fazio et al. also discloses programming a flash memory cell to one of at least three amounts of charge, wherein the amount of charge placed in the flash memory cell is increased by increasing the voltage level of a programming pulse applied to the memory cell.
U.S. Pat. No. 5,574,879 to Wells et al. discloses addressing modes for a dynamic single bit per cell to multiple bit per cell memory. Wells et al. also discloses a memory system containing switch control for selecting between standard cell addressing modes and multi-level cell addressing modes. U.S. Pat. No. 5,594,691 to Bashir discloses address transition detection sensing circuitry for flash memory having multi-bit cells and methods for using same. U.S. Pat. No. 5,612,912 to Gillingham discloses a method of sensing and restoring voltages in a multi-level DRAM cell.
However, none of these patents appears to disclose memory devices, apparatuses, systems and methods of using multi-bit memory cells to provide parity bits or methods of storing and retrieving partial bits of data from a single memory cell. Thus, there exists a need in the art for memory devices, apparatuses, systems and methods of using multi-bit memory cells to provide parity bits in a memory device based on multiples of 8 bits.